Fault Coverage Requirement in Production Testing of LSI Circuits

A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips. It is based on a model for the distribution of faults on a chip. The model requires two parameters, the average number (n0) of faults on a faulty chip and the yield (y) of good chips. It is assumed that the yield either is known or can be calculated from the available formulas. The other parameter, n0, is determined from an experimental procedure. Once the model is fully characterized, it allows calculation of the field reject rate as a function of the fault coverage. The technique implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment. An actual LSI circuit is used as an example

Fault Coverage Requirement in Production Testing of LSI Circuits

A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips. It is based on a model for the distribution of faults on a chip. The model requires two parameters, the average number (n0) of faults on a faulty chip and the yield (y) of good chips. It is assumed that the yield either is known or can be calculated from the available formulas. The other parameter, n0, is determined from an experimental procedure. Once the model is fully characterized, it allows calculation of the field reject rate as a function of the fault coverage. The technique implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment. An actual LSI circuit is used as an example

Parallel Test Generation With Low Communication Overhead

In this paper we present a method of parallelizing test generation for combinational logic using boolean satisfiability. We propose a dynamic search-space allocation strategy to split work between the available processors. This strategy is easy to implement with a greedy heuristic and is economical in its demand for inter-processor communication. We derive an analytical model to predict the performance of the parallel versus sequential implementations. The effectiveness of our method and analysis is demonstrated by an implementation on a Sequent (shared memory) multiprocessor. The experimental data shows significant performance improvement in parallel implementation, validates our analytical model, and allows predictions of performance for a range of time-out limits and degrees of parallelism

DynaTAPP Dynamic Timing Analysis With Partial Path Activation in Sequential Circuits

This paper gives a method of finding all sensitizable paths in a non-scan synchronous sequential circuit. Path activation conditions of the circuit are mapped onto a single stuck type fault by adding a few modeling gates to the netlist. Only if the corresponding stuck type fault is found detectable by a sequential circuit test generator is the path considered sensitizable. A depth-first analysis of circuit topology, that determines all paths between primary inputs, primary outputs and flip-flops, employs a partial path hierarchy. Thus, all paths with a common unsensitizable segment need not be examined separately. Results on benchmark circuits show that ( I ) the number of sensitizable paths can be significantly smaller than that found by a static timing analyzer and (2) the partial path analysis adds to efficiency when the number of sensitizable paths is less than 20 percent

Generating Tests for Delay Faults in Nonscan Circuits

This new method allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits. To test a given path, the authors augment the netlist model of the circuit with a logic block in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. The authors present results on benchmarks for nonscan and scan/hold modes of testing

High-Level Microprogramming: An Optimising C Compiler for a Processing Element of a CAD Accelerator

The development of a high-level language compiler for a micro-programmable processing element (PE) in the MARS multicomputer is described. MARS, an MIMD message passing machine, was designed to speed up VLSI CAD and similar other non-numerical applications. The need for sup port of a high-level language at the PE level of a multicomputer is considered, and the choice of C as an appropriate programming language is justified. Special features found in VLSI processors are examined along with compiler support for them. Conventional re-targetable compiler techniques are shown to be inadequate for the highly concurrent micro-programmable PE. These techniques must be extended for microcode generation. The design of the MARS compiler is outlined. Performance data is provided to evaluate the benefit of various compiler optimizations, and to compare compiler generated microcode to hand generated microcode in terms of space and time performanc

Network-layer and link-layer use of shadow addresses in soft handoff within subnets

[[abstract]]A technique for assigning an address ("shadow address") to a mobile station that is compatible with the layer-2 address on the wireline network which serves the mobile station. The shadow address is then used as a wireline identifier for the destination address for frames ultimately destined for the mobile station. The shadow address is stored in a watch list for serving base stations, and any base station receiving a frame with a shadow address in its watch list process the frame to forward it the to mobile station. In this way, the shadow address facilitates carrying out soft handoff and smooth handoff.[[department]]資工